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December 19, 2012
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News for and about the microelectronics industry

  Today's Tech Buzz 
  • FTC opposes IDT's acquisition of PLX
    Integrated Device Technology's proposed acquisition of PLX Technology would give the combined company more than 85% of the PCIe switch chip market, according to the Federal Trade Commission, leading the regulator to oppose the $330 million purchase. "The combination of IDT and PLX would hurt competition and lead to higher switch prices, lower innovation in the marketplace and reduced customer service," FTC's Richard Feinstein said. Reuters (12/19) LinkedInFacebookTwitterEmail this Story
  ICs, Memory & More 
  • Will "Azalea" bloom into a big wafer fab for Oregon or New York?
    Officials in Oregon are trying to lure a semiconductor manufacturer, code-named Azalea, into building a wafer fabrication facility in the Beaver State, The Oregonian reports. The same chipmaker is being courted by New York state, the newspaper says, citing a person with knowledge of Azalea but not authorized to speak about it. That chipmaker may be Taiwan Semiconductor Manufacturing, according to various media reports. The Oregonian (Portland) (12/18) LinkedInFacebookTwitterEmail this Story
  • EU official envisions a continental chip company
    EU Commissioner Neelie Kroes says Europe may have to emulate the example of aircraft manufacturer Airbus by building a continental semiconductor company. "Why not a digital Airbus, or an Airbus for the chip sector?" Kroes says. "That scale of success is what you can get if you put borders aside and work in partnership." News Service (12/18) LinkedInFacebookTwitterEmail this Story
  • Other News
  Going Green 
  • Report: Nvidia's "Wayne" processor will have 4 Cortex-A15 cores
    The fourth-generation "Wayne" processor is said to have four ARM Cortex-A15 cores, a new GeForce graphics processor and a new memory controller, according to a presentation slide published by the ChipHell website. The new chip will be used in advanced smartphones and tablet computers. Nvidia didn't comment on the report. (12/18) LinkedInFacebookTwitterEmail this Story
  • Low-power DRAM from Hynix has new process integration scheme
    The H5TC2G83CFR-H9R memory chip made by SK Hynix, a 2-gigabit DDR3 synchronous DRAM, features a "significantly different" process integration scheme compared with earlier Hynix memory chips, according to Arabinda Das of UBM TechInsights, which conducted a structural analysis of the low-power device. "Surprisingly, the wordline pitch measured in the bitline direction was found to be the same as in the previous generation Hynix 44-nanometer 2-Gbit DDR3 SDRAM, which was measured to be 88nm," Das writes. EE Times (12/18) LinkedInFacebookTwitterEmail this Story
Register now for JEDEC's DDR4 Workshop:
Early Bird Discounts end Friday

Register today to reserve your spot in Santa Clara, CA for a 2-day, in-depth technical review of the new DDR4 standard on 2/6 & 2/7, taught by industry experts involved in the creation of the standard. Space is very limited — see the agenda and REGISTER NOW for the DDR4 Workshop.
  Semiconductors in Action 
  • Will Nvidia stack graphics chips for Apple computers?
    Nvidia conceivably could stack two to four graphics processing units in one package to offer Apple more powerful capabilities for its iMac, iPad and MacBook computers, Rick Merritt speculates in this article. "It might even add a memory chip to the mix to create a device with fast memory access, good for either an iMac or [a] MacBook," he notes. EE Times (12/18) LinkedInFacebookTwitterEmail this Story
  • Other News
  Testing & Standards 
  • GlobalFoundries may turn to SSRW tech as successor to CMOS
    GlobalFoundries is considering use of super-steep retrograde well technology as a potential replacement for bulk planar complementary metal-oxide semiconductor processes, according to this article. A fabless semiconductor company, SuVolta, has developed such technology, but a spokesman for the silicon foundry declined to comment on whether GlobalFoundries is collaborating with SuVolta. EE Times (12/18) LinkedInFacebookTwitterEmail this Story
  JEDEC News 
  • LAST CHANCE to save with early bird discounts: JEDEC DDR4 Workshop
    Register by 12/21 for best savings -- $50 off onsite rates -- for JEDEC's two-day DDR4 Workshop on Feb. 6 and 7 in Santa Clara, Calif. This event will offer an in-depth technical review of DDR4, as taught by industry experts involved in the creation of the standard. Participants will gain insight into DDR4's wide range of innovative features and device operation, as well as current and planned technological enablements to facilitate adoption of DDR4. See the agenda and register today -- space is very limited. LinkedInFacebookTwitterEmail this Story
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products now available for free download
    JEP95 is a compilation of some 3000 pages of outline drawings for microelectronic packages. In addition to the free downloads available on the JEDEC website, an annual updating service and complete hard copies are available for purchase. Recent updates include: MO-269H, Registration - DDR3 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers and MO-274C, Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. LinkedInFacebookTwitterEmail this Story
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To be without some of the things you want is an indispensable part of happiness."
--Bertrand Russell,
British philosopher, mathematician and historian

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