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November 13, 2012
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News for and about the microelectronics industry

  Today's Tech Buzz 
  • Everspin rolls out Spin-Torque MRAMs
    Everspin Technologies has introduced what it calls, Spin-Torque magnetoresistive random-access memory chips, 64-megabit DDR3 memories that could present an alternative to existing memory types. While these MRAMs offer less data-storage capability than DRAMs or flash memory devices, they are said to provide faster data transfer at lower energy consumption. "We are collaborating with select customers to allow them to evaluate and take advantage of Spin-Torque MRAM technology sooner and to gather feedback that will help us finalize our 64Mb DDR3 ST-MRAM for production," said Everspin President and CEO Phill LoPresti. VentureBeat (11/12), Computerworld (11/12) LinkedInFacebookTwitterEmail this Story
  ICs, Memory & More 
  • ARM CEO: Microcontrollers could have multiple cores
    Microprocessors, especially those for mobile electronics, contain multiple cores these days, and that trend is likely to spread to their less sophisticated cousins, microcontrollers, according to ARM Holdings CEO Warren East. "That alone would double the market size for ARM," he says in this interview, adding, "The Internet of Things for us is about the sale of microcontrollers. We think it is likely to follow a similar path to mobile phones." EE Times (11/12) LinkedInFacebookTwitterEmail this Story
  • Other News
  Going Green 
  • ST offers kit for battery-free electronics
    The new M24LR Discovery kit from STMicroelectronics contains two boards, one of which runs on radio-frequency identification readers or smartphones with near-field communication capability. The M24LR board contains ST's M24LR04E-RMN6T/2 Dual Interface EEPROM for energy-harvesting applications. EE Times (11/12) LinkedInFacebookTwitterEmail this Story
  Semiconductors in Action 
  • TI debuts quad-core processor for modeling applications
    Texas Instruments has introduced the 66AK2H12 processor, which contains four 1.4GHz ARM Cortex-A15 processor cores and eight 1.2GHz TMS320C66x digital signal processor cores. The chip can be used for gaming and for modeling in financial services, oil and gas exploration and weather forecasting, according to TI. Electronics Weekly (U.K.) (11/13) LinkedInFacebookTwitterEmail this Story
  • Intel sets out roadmap for Itanium and Xeon processors
    Future versions of the Itanium processor are expected to use the same chipsets, motherboards and processor sockets as Intel's more popular Xeon processors, ExtremeTech reports. This transition could occur in 2014 or later, after the chipmaker brings out its Xeon server chips with the Haswell microarchitecture, this blog post notes. Ars Technica (11/12) LinkedInFacebookTwitterEmail this Story
  • AMD, Nvidia introduce supercomputing GPUs
    Advanced Micro Devices has introduced the FirePro SM10000 graphics processing unit for high-performance computers and virtual servers, while Nvidia debuted the K20 and K20X GPUs. The K20X is being used in Titan, currently the world's fastest supercomputer, installed at the Oak Ridge National Laboratory. Network World/IDG News Service (11/12) LinkedInFacebookTwitterEmail this Story
  Testing & Standards 
  • Electronic design with SAR-ADCs
    The use of successive-approximation register analog-to-digital converters in medium-resolution applications is discussed by Bonnie Baker of Texas Instruments in this technical article. Existing SAR-ADCs can range in resolution from 8 bits to 18 bits, she notes. EE Times (11/12) LinkedInFacebookTwitterEmail this Story
  JEDEC News 
  • JEDEC announces the publication of LPDDR2/3 I/O standard
    JESD8-22A, HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT is now available for free download on the JEDEC website. This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. LinkedInFacebookTwitterEmail this Story
  • JEDEC and ONFI publish NAND flash interface interoperability standard
    JEDEC and the Open NAND Flash Interface Workgroup (ONFI) have announced the publication of JESD230 NAND Flash Interface Interoperability Standard (Package). This jointly developed document defines a standard for NAND flash device interface interoperability. JESD230 is available for free download from both and LinkedInFacebookTwitterEmail this Story
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