Intel has established the Artificial Intelligence Products Group, pulling together its AI efforts in one organization, including chips by Movidius and Nervana Systems, companies Intel acquired in 2016. Naveen Rao, the former Nervana CEO, will serve as vice president and general manager of the new group.
Researchers at Los Alamos National Laboratory report identifying "very fast electron trapping by defect-related states" as the source of energy-conversion inefficiency in quantum dot solar cells, Steve Bush writes. The discovery is expected to improve the 10% efficiency of such cells.
While the Semiconductor Industry Association forecasts worldwide chip sales will increase 3.3% this year to about $346 billion, there are numerous challenges to designing and producing ICs, Ed Sperling writes. These factors include safety-critical design, scaling problems and industry inertia.
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Register by May 8 to save $25-50 over onsite rates! Join us for the 32nd Annual ROCS Workshop on May 22 in Palm Springs, CA, co-located with CS ManTech. Papers presenting the latest results and new developments in all phases of compound semiconductor reliability will be presented.
The emerging portable stimulus standard was the topic of a panel session at the recent DVCon. "It is [a] privilege to work with the people on the committee, who are incredibly smart and have passion and are doing really good work, but at the same time it is very frustrating," said Dave Brownell of Analog Devices.
Product engineers at Maxim Integrated play several roles in the transition between chip design and fabrication, Martin Rowe writes. Among their duties is testing the "first silicon" from the wafer fab, working with the design engineers.
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. For more information and free download, visit the JEDEC website.